Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Multiple patterning techniques are now commonly employed to increase the resolution of features printed onto the semiconductor wafer for a given lithographic system. FIGS. 1A-1D depict a double patterning lithography (DPL) technique commonly referred to as a litho-etch-litho-etch (LELE) process. FIG. 1A depicts a silicon base layer 10, an interface layer such as silicon dioxide, a device layer 12, a hard mask layer 13, a sacrificial layer 14, and a patterned resist layer 15 that results from a lithography patterning step. The structure of depicted in FIG. 1A is then subjected to exposure and etch steps that result in the structure illustrated in FIG. 1B. In this structure, the pattern of resist layer 15 has been effectively transferred to the hard mask layer 13. Both the sacrificial layer 14 and the patterned resist layer 15 have been removed. A number of deposition and lithographic steps are employed to arrive at the structure illustrated in FIG. 1C. FIG. 1C illustrates another sacrificial layer 16 and patterned resist layer 17 built on top of the hard mask layer 13. Patterned resist layer 17 includes a pattern having the same pitch as the first patterned resist layer 15, and also the same pitch as the pattern etched into the hard mask layer 13. However, the patterned resist layer 17 is offset from the pattern of the hard mask layer 13 by half of the pitch of the patterned resist layer 17. The structure of depicted in FIG. 1C is then subjected to exposure and etch steps that result in the structure illustrated in FIG. 1D. In this structure, the pattern of resist layer 17 has been effectively transferred to the hard mask layer 13. Both the sacrificial layer 16 and the patterned resist layer 17 have been removed. FIG. 1D illustrates a pattern etched into hard mask 13 that is double the pitch of the patterned resist layers 15 and 17 generated by the mask of the lithographic system.
FIG. 1D also depicts the effects of a non-optimized DPL process. Ideally, the nominal pitch of the double patterned structure should be a constant value, P. However, due to imperfections in the DPL process, the pitch of the resulting structure may vary depending on location due to grating non-uniformities. This is commonly termed “pitch walk.” A variation from the nominal pitch, P, is depicted as ΔP in FIG. 1D. In another example, a critical dimension of each resulting structure should be the same nominal value, CD. However, due to imperfections in the DPL process, a critical dimension (e.g., middle critical dimension, bottom critical dimension, etc.) of the resulting structure may vary depending on location. A variation from the critical dimension, CD, is depicted as ΔCD in FIG. 1D.
Pitch walk and ΔCD are exemplary geometric errors induced by imperfections in the DPL process such as misalignment between the two lithography layers, non-uniformities in the focus and exposure of the lithographic process, mask pattern errors, etc. Both pitch walk and ΔCD introduce a unit cell that is larger than expected. Although pitch walk and ΔCD are described in particular, other multiple patterning errors may be contemplated.
Although the LELE process is described with reference to FIGS. 1A-1D, many other multiple patterning processes that induce similar errors may be contemplated (e.g., litho-litho-etch, spacer defined double patterning, etc.). Similarly, although a double patterning process is described with reference to FIGS. 1A-1D, similar errors arise in higher order patterning processes such as quadruple patterning. Typically, errors such as pitch walk and ΔCD are more pronounced in structures that result from higher order patterning processes.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput measurement without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition and other parameters of nanoscale structures.
However, measurement of errors induced by multiple patterning processes is especially challenging due to the fact that optical CD, and even CD-SEM measurements, lack significant sensitivity to these types of errors.
Metrology applications involving the measurement of structures generated by multiple patterning processes present challenges due to increasingly small resolution requirements, multi-parameter correlation, increasingly complex geometric structures, and increasing use of opaque materials. Thus, methods and systems for improved measurements are desired.